DocumentCode :
2296654
Title :
Accuracy sensitive word-length selection for algorithm optimization
Author :
Wadekar, Suhrid A. ; Parker, Alice C.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1998
fDate :
5-7 Oct 1998
Firstpage :
54
Lastpage :
61
Abstract :
In typical hardware implementations of an arithmetic-intensive algorithm, designers must determine the word lengths of resources such as adders, multipliers, and registers. This paper presents algorithmic level theory and optimization techniques to select distinct word lengths for each computation which meet the desired accuracy and minimize the design cost for the given performance constraints. The reduction in cost is possible by avoiding unnecessary bit-level computations that do not contribute significantly to the accuracy of the final results. Thus we have introduced a new optimization variable, computation accuracy, into data-path synthesis. Our results show on an average, a 30% reduction in functional-resource area using distinct word lengths as opposed to use of a single optimized word length for the entire algorithm
Keywords :
adders; digital arithmetic; logic design; accuracy sensitive word-length selection; adders; algorithm optimization; algorithmic level theory; arithmetic-intensive algorithm; bit-level computations; data-path synthesis; hardware implementations; multipliers; optimization techniques; performance constraints; registers; Algorithm design and analysis; Arithmetic; Clustering algorithms; Computer architecture; Cost function; Design optimization; Government; Manuals; Multiplexing; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-8186-9099-2
Type :
conf
DOI :
10.1109/ICCD.1998.727023
Filename :
727023
Link To Document :
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