• DocumentCode
    2296716
  • Title

    Multiple-valued logic design using multiple-valued EXOR

  • Author

    Hozumi, Takahiro ; Kamiura, Naotake ; Hata, Yutaka ; Yamato, Kazuharu

  • Author_Institution
    Fac. of Eng., Himeji Inst. of Technol., Japan
  • fYear
    1995
  • fDate
    23-25 May 1995
  • Firstpage
    290
  • Lastpage
    294
  • Abstract
    An approach to logic minimization using a new sum operation called multiple valued EXOR is proposed. The paper introduces the multiple valued sum of products expression using the EXOR. As the scheme of the minimization, we utilize an idea based on neural computing. First, we demonstrate the method to minimize the binary EXOR of MINs expressions and show that the method is effective. Next, we apply the method to the three valued EXOR of MINs expression. Experimental results for all three valued two variable functions show that our proposed multiple valued EXOR of MINs expressions require fewer product terms than both the MAX of MINs and TSUM of MINs expressions
  • Keywords
    logic design; minimisation of switching nets; multivalued logic; neural nets; MAX of MINs; TSUM of MINs expressions; binary EXOR of MINs expressions; logic minimization; multiple valued EXOR of MINs expressions; multiple valued logic design; multiple valued sum of products expression; multiple-valued EXOR; multiple-valued logic design; neural computing; sum operation; three valued EXOR of MINs expression; three valued two variable functions; Arithmetic; Circuits; Computer networks; Logic design; Logic functions; Logic gates; Logic testing; Minimization methods; Neurons; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 1995. Proceedings., 25th International Symposium on
  • Conference_Location
    Bloomington, IN
  • ISSN
    0195-623X
  • Print_ISBN
    0-8186-7118-1
  • Type

    conf

  • DOI
    10.1109/ISMVL.1995.513545
  • Filename
    513545