FPGA Based Reconfigurable 200 MHz Transmitter and Receiver Front End for MIMO-OFDM

This paper focuses on design, implementation and optimization of digital front end module of Multiple Input Multiple Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) system on FPGA employing Alamouti Technique (Space Time Block coding). MIMO-OFDM can very effectively be used to achieve higher data rates and higher reliability and this is going to be the Key for 4G Technology. MIMO-OFDM designed in this work consists of Input/Output memory, 16-QAM modulator, MIMO Encoder( Space Time Encoder), Wireless Channel Model, MIMO Decoder( Space Time Decoder) and 16-QAM Demodulator. This paper has resulted in the development of a hardware prototype of a MIMO Transmitter, Receiver and channel, which works at the speed of 200MHz on a Spartan-3 FPGA board. Test benches for individual model were developed and tested it for its correct functionality. The functional simulation was carried out for the entire design. The entire design was mapped on to FPGA.