Title :
Circuit implementation of a 600 MHz superscalar RISC microprocessor
Author :
Matson, M. ; Bailey, D. ; Bell, S. ; Biro, L. ; Butler, S. ; Clouser, J. ; Farrell, J. ; Gowan, M. ; Priore, D. ; Wilcox, K.
Author_Institution :
Compaq Comput. Corp., Shrewsbury, MA, USA
Abstract :
The circuit techniques used to implement a 600 MHz, out-of-order, superscalar RISC Alpha microprocessor are described. Innovative logic and circuit design created a chip that attains 30+ SpecInt95 and 50+ SpecFP95, and supports a secondary cache bandwidth of 6.4 GB/s. Microarchitectural techniques were used to optimize latencies and cycle time, while a variety of static and dynamic design methods balanced critical path delays against power consumption. The chip relies heavily on full custom design and layout to meet speed and area goals. An extensive CAD suite guaranteed the integrity of the design
Keywords :
delays; logic design; microprocessor chips; power consumption; reduced instruction set computing; 30+ SpecInt95; 50+ SpecFP95; 600 MHz superscalar RISC microprocessor; Alpha microprocessor; CAD suite; circuit implementation; critical path delays; cycle time; latencies; logic and circuit design; microarchitectural techniques; power consumption; secondary cache bandwidth; Bandwidth; Circuit synthesis; Delay; Design optimization; Logic circuits; Logic design; Microarchitecture; Microprocessors; Out of order; Reduced instruction set computing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-9099-2
DOI :
10.1109/ICCD.1998.727030
