Area-oriented synthesis for pass-transistor logic

Pass Transistor Logic (PTL) circuits have been successfully used to implement digital ICs which are smaller, faster, and more energy efficient than static CMOS implementations of the same designs. Thus far, most PTL implementations have been handcrafted; as such, designer acceptance of PTL has been limited. In this paper, we develop efficient algorithms for automated synthesis of high quality PTL designs. Our approach is based on the use of Binary Decision Diagrams (BDDs) to represent logic functions. We present several BDD optimization techniques targeting minimum area PTL implementations. We compare our results with prior work on PTL synthesis; we also provide comparison between synthesized static CMOS and synthesized PTL at the layout level for control logic from a commercial microprocessor