Title :
Re-synthesis in technology mapping for heterogeneous FPGAs
Author :
Inuani, Maurice ; Saul, Jonathan
Author_Institution :
Comput. Lab., Oxford Univ., UK
Abstract :
Field programmable gate arrays containing more than one size of lookup-table occupy a large and growing portion of the market, but technology mapping for these architectures has hardly been considered. New algorithms have been developed for decomposition, covering and restructuring targeted at these architectures. Benchmark results show that the new method produces circuits which are on average 15% smaller than the best previous approach we know of
Keywords :
field programmable gate arrays; logic design; logic testing; performance evaluation; table lookup; benchmark results; decomposition; field programmable gate arrays; heterogeneous FPGAs; lookup-table; technology mapping resynthesis; Consumer electronics; Cost function; Field programmable gate arrays; Integrated circuit interconnections; Laboratories; Logic circuits; Programmable logic arrays; Prototypes; Reconfigurable logic; Table lookup;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-9099-2
DOI :
10.1109/ICCD.1998.727047
