DocumentCode :
2297160
Title :
Clock-skew constrained placement for row based designs
Author :
Venkateswaran, Natesan ; Bhatia, Dinesh
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
fYear :
1998
fDate :
5-7 Oct 1998
Firstpage :
219
Lastpage :
220
Abstract :
In this paper we address the problem of placement of standard cells under the constraints of minimizing the clock-skew. We propose a quadratic programming based methodology for placement that not only results in an area and timing wise good placement but also a supporting zero-skew clock routing tree. Under the clock-skew constraints, our method produces significant reduction in the cost of zero-skew clock routing tree. During placement, we are able to obtain significant speed-up due to variable reduction and constraint modification
Keywords :
VLSI; cellular arrays; circuit layout CAD; logic CAD; quadratic programming; timing; clock-skew constrained placement; quadratic programming based methodology; row based designs; standard cells; zero-skew clock routing tree; Circuits; Clocks; Costs; Delay effects; Delay estimation; Electronic switching systems; Quadratic programming; Routing; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-8186-9099-2
Type :
conf
DOI :
10.1109/ICCD.1998.727053
Filename :
727053
Link To Document :
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