AMULET3: a high-performance self-timed ARM microprocessor

Author

Furber, S.B. ; Garside, J.D. ; Gilbert, D.A.

Author_Institution

Dept. of Comput. Sci., Manchester Univ., UK

fYear

1998

fDate

5-7 Oct 1998

Firstpage

247

Lastpage

252

Abstract

AMULET3 is a fully asynchronous implementation of ARM architecture v4T and was designed at the University of Manchester between 1996 and 1998. It is the third generation asynchronous ARM, and is aimed at a significantly higher performance level than its predecessors. Achieving this higher performance has required significant enhancements to the internal micro-architecture, such as the introduction of a reorder buffer to support efficient forwarding while retaining exact exception handling. In this paper we present an overview of the AMULET3 core, highlighting the issues which arise when striving for high performance and instruction set compatibility in an asynchronous design framework

Keywords

computer architecture; exception handling; microprocessor chips; AMULET3; ARM architecture; asynchronous ARM; asynchronous design framework; exact exception handling; instruction set compatibility; micro-architecture; performance; reorder buffer; Circuits; Clocks; Computer architecture; Computer science; Electromagnetic compatibility; Energy management; Industrial electronics; Microprocessors; Random access memory; Technology management;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-9099-2

Type

conf

DOI

10.1109/ICCD.1998.727058

Filename

727058