Design issues in mixed static-domino circuit implementations

Due to its performance advantage, domino logic has been extensively used to implement critical paths in advanced microprocessor designs. Since domino circuits are employed in a mainly static environment, static logic imposes strict timing constraints on domino logic and its use. In this paper, we present the design issues involved in implementing mixed domino and static logic circuits in high performance microprocessors designs. These issues are addressed with design guidelines in a custom design methodology. Simulations of some designs with mixed static-domino implementations show that static-domino interface can severely constrain their performance. To alleviate this bottleneck, we reanalyze the interaction between static and domino signals in detail and a new relaxed static-domino interface constraint is derived. This new relaxed constraint can result in a significant performance improvement of mixed static-domino implementations