Low-loss 0.13-µm CMOS 50 – 70 GHz SPDT and SP4T switches

This paper presents 50-70 GHz single-pole double-throw (SPDT) and single-pole four-throw (SP4T) switches built using a low-cost 0.13-Mm CMOS process. The switches are based on tuned lambda/4 designs with output matching networks. High substrate resistance together with deep trenches and isolation moats are used for low insertion loss. The SPDT and SP4T switches result in a measured insertion loss of 2.0 and 2.3 dB at 60 GHz, with an isolation of Gt 32 dB and Gt 22 dB, respectively. The measured output port-to-port isolation is Gt 27 dB for both designs. The P1dB is 13-14 dBm with a measured IIP3 of Gt 23 dBm for both switches. Both designs have a return loss better than -10 dB at all ports from 50 to 70 GHz. The active chip area is 0.39times0.32 mm² (SPDT) and 0.59times0.45 mm² (SP4T). To our knowledge, this paper presents the lowest loss 60 GHz SPDT and SP4T switches and also the highest isolation SPDT switch in any CMOS technology to-date.