Video DSP architecture and its application design methodology for sampling rate conversion

Author

Nakamura, Ken´ichiro ; Kurokawa, Masuyoshi ; Hashiguchi, Akihiko ; Kanou, Mamoru ; Aoyama, Koji ; Okuda, Hiroshi ; Iwase, Seiichiro ; Yamazak, Takao

Author_Institution

Media Process. Labs., Sony Corp., Tokyo, Japan

fYear

1996

fDate

30 Oct-1 Nov 1996

Firstpage

418

Lastpage

427

Abstract

This paper describes the special architecture of the linear array DSP and design methodology for the application to convert sampling rate of the video signals. This methodology allows us to develop a detailed DSP application code for a given sampling conversion rate. Compared to the ASIC implementation of sampling rate conversion, the required time for implementation is drastically reduced. An example of conversion from HDTV to SDTV (wide) is given

Keywords

digital filters; high definition television; parallel architectures; signal sampling; video signal processing; ASIC implementation; DSP application code; HDTV; SDTV; design methodology; filter design; implementation time reduction; linear array DSP; sampling rate conversion; video DSP architecture; video signals; Application specific integrated circuits; Computer displays; Design methodology; Digital signal processing; HDTV; Laboratories; Process control; Sampling methods; Streaming media; TV;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, IX, 1996., [Workshop on]

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-3134-6

Type

conf

DOI

10.1109/VLSISP.1996.558374

Filename

558374