DocumentCode
2297346
Title
Pipelined computation of LNS addition/subtraction with very small lookup tables
Author
Chen, Chichyang ; Yang, Chih-Huan
Author_Institution
Dept. of Inf. Eng., Feng Chia Univ., Taichung, Taiwan
fYear
1998
fDate
5-7 Oct 1998
Firstpage
292
Lastpage
297
Abstract
Logarithmic number system (LNS) has the advantages of regular data flow high speed, and high precision. However, the development of LNS arithmetic is hindered by the large size of the lookup tables used in LNS addition/subtraction, since the size is exponentially proportional to the word length of the operands. To overcome this large-table problem, LNS addition/subtraction is proposed to be computed in a pipelined manner. The computation includes an exponential stage and a logarithmic stage. The exponential stage is implemented by using digit-parallel additive normalization and the logarithmic stage is implemented by using digit on-line multiplicative normalization. It has been computed that the size of the lookup tables used in a 33-bit LNS unit is about 0.543 Mbits, which is very small. The hardware cost of the other circuits in this LNS unit is only linearly proportional to the word length of the operands. We conclude that the proposed method makes large word-length LNS arithmetic possible
Keywords
digital arithmetic; pipeline arithmetic; table lookup; LNS arithmetic; large word-length; logarithmic number system; lookup tables; pipelined; Arithmetic; Computer architecture; Costs; Data engineering; Dynamic range; Equations; Microwave integrated circuits; Strontium; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-9099-2
Type
conf
DOI
10.1109/ICCD.1998.727064
Filename
727064
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