Partitioning in time: a paradigm for reconfigurable computing

In recent years, we have witnessed the rapid growth of reconfigurable computers. The first generation of reconfigurable computers consists of multiple FPGAs interconnected in a network. The computations are performed by partitioning an entire task into spatially interconnected sub-tasks. FPGAs used in the reconfigurable computers are programmed only once during the runtime of an executing application. FPGAs have the ability to reconfigure rapidly to any desired custom form. Reusing the FPGA resources during the application runtime can yield cost effective solutions for reconfigurable computing. Such runtime reconfiguration of FPGAs requires an efficient framework for the analysis and synthesis of the application and tools that handle the runtime reconfiguration. In this paper, we introduce the concept of temporal partitioning, to partition a task into temporally interconnected sub-tasks. We present algorithms and methodologies to analyze an application, and techniques to reuse the programmable hardware during the runtime of the application. Our approach has been successfully tested on read applications and has proven to be cost effective