Low-voltage, inductorless folded down-conversion mixer in 65nm CMOS for UWB applications

Author

Hampel, S.K. ; Schmitz, O. ; Tiebout, M. ; Rolfes, I.

Author_Institution

Inst. of Radiofreq. & Microwave Eng., Leibniz Univ. Hannover, Hannover, Germany

fYear

2009

fDate

7-9 June 2009

Firstpage

119

Lastpage

122

Abstract

This paper presents the design and implementation of a low-voltage down-conversion mixer in 65 nm CMOS technology for UWB applications. The folded circuit topology with AC-coupled inverter based RF transconductance stage operates under low voltage conditions of 1.2 V with a peak gain of 14.5 dB and a 3-dB-bandwidth from 1 GHz to 10.5 GHz with 1 dBm LO power. The input referred compression point is better than -16.5 dBm with an oIP3 of 7 dBm at 2 GHz. The minimum DSB noise figure is 6.5 dB with a flicker-noise corner frequency of 2 MHz. The mixer draws 12 mA from a power supply of 1.2 V leading to a power dissipation of only 14.4 mW.

Keywords

CMOS analogue integrated circuits; MMIC mixers; UHF integrated circuits; UHF mixers; field effect MMIC; flicker noise; network topology; ultra wideband technology; AC-coupled inverter; CMOS; RF transconductance; UWB applications; current 12 mA; flicker-noise; folded circuit topology; frequency 1 GHz to 10.5 GHz; frequency 2 MHz; gain 14.5 dB; low-voltage down-conversion mixer; noise figure 6.5 dB; power 14.4 mW; power dissipation; size 65 nm; voltage 1.2 V; CMOS technology; Circuit topology; Gain; Inverters; Low voltage; Noise figure; Power dissipation; Power supplies; Radio frequency; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE

Conference_Location

Boston, MA

ISSN

1529-2517

Print_ISBN

978-1-4244-3377-3

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2009.5135503

Filename

5135503