DocumentCode :
2297661
Title :
Incorporating timing constraints in the efficient memory model for symbolic ternary simulation
Author :
Velev, Miroslav N. ; Bryant, Randal E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
1998
fDate :
5-7 Oct 1998
Firstpage :
400
Lastpage :
406
Abstract :
This paper introduces the four timing constraints of setup time, hold time, minimum delay, and maximum delay in the efficient memory model (EMM). The EMM is a behavioral model, where the number of symbolic variables used to characterize the initial state of the memory is proportional to the number of distinct symbolic memory locations accessed. The behavioral model provides a conservative approximation of the replaced memory array, while allowing the address and control inputs of the memory to accept symbolic ternary values. If a circuit has been formally verified with the behavioral model, the system is guaranteed to function correctly with any memory implementation whose timing parameters are bounded by the ones used in the verification
Keywords :
delays; formal verification; logic CAD; timing; behavioral model; hold time; maximum delay; memory model; minimum delay; setup time; symbolic ternary simulation; timing constraints; timing parameters; Circuit simulation; Computational modeling; Computer science; Computer simulation; Delay effects; Digital circuits; Hazards; Time factors; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-8186-9099-2
Type :
conf
DOI :
10.1109/ICCD.1998.727081
Filename :
727081
Link To Document :
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