NMOS and PMOS Translinear Multiplying Cell for Current-Mode Signal Processing

The paper describes NMOS and PMOS translinear cell which multiplies the current signals and which can be used for the current-mode signal processing. The translinear cell consists of NMOS or PMOS transistors that are treated in the sub-threshold conduction region. In this region the transistors exhibit an exponential dependency of the drain current versus the gate voltage and thus the translinear principle can be used for description of the functionality. Operation region of the cell is limited by the validity of the exponential dependency and also by the transistors leakage currents. Significant error is also induced by the auxiliary current mirrors which are biasing the cells. Channel length modulation effect causes error of the input signals and thus the output signal is affected by the multiplicative error. The paper presents basic idea of the multiplying cell, presents results of simulations in CADENCE and also presents results of measurements on real structure composed using discrete transistors.