3D modeling and finite-element full-wave simulation of TSV for stack up SIP integration applications

The modeling and simulation of via´s effect on the data transferring or high frequency signal path and device performance have been one of the major concerns in the designing and testing of multilayered electric interconnects in applications like highly integrated system-in-package (SIP) and high-speed circuitry design. The authors of this paper explore the 3D full-wave modeling of through Si vias (TSV) in multilayered SIP and simulate their effects on spectral performance and signal integrity with the help of finite element methodologies. The emphasis of the research is on the revealing of 3D electromagnetic field distribution on fundamental single and differential TSV interlayer interconnects, so that more detailed parasitic effects may be found and equivalent model closer to the reality can be obtained, compared with the methodology based on purely circuit analysis. And the effect of the variations in the TSV diameter and height and the effect of grounded TSV are revealed. Additionally, S21 performance and field distribution of two sort of paired vias are displayed. Waveports are adopted for the full-wave modeling and all the cases are in 0~10GHz range.