DocumentCode
2298166
Title
Code coalescing unit: a mechanism to facilitate load store data communication
Author
John, Lizy ; Teh, Yin ; Matus, Francis ; Chase, Craig
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear
1998
fDate
5-7 Oct 1998
Firstpage
550
Lastpage
557
Abstract
Program behavior studies demonstrate that a significant fraction of load instructions in a program read the data stored by an instruction in the immediate past. In this paper, we propose a scheme entitled the Code Coalescing Unit that eliminates several of the memory access instructions by buffering the data in a Store Register Rename Buffer (SRRB) which is similar to the store buffer and renaming the instructions that use the data to access it directly from the buffer. The Code Coalescing Unit (CCU) can be considered as an extension to the fill unit proposed by S.W. Melvin et al. (1988). Their fill unit groups together micro-operations into larger atomic units and stores them into the decoded instruction cache (DIC) which are later executed directly from the DIC. The original fill unit grouped together micro-operations into larger atomic units, but the proposed Code Coalescing Unit goes further by eliminating particular load operations in the process of grouping together micro-operations. Experiments on eight applications including Microsoft Word for Windows, Microsoft C++ compiler and two SPEC programs demonstrate that approximately 25%, 34% or 42% of all load operations performed by these applications could have been eliminated using a Code Coalescing Unit in conjunction with a Store Register Rename Buffer of 8, 16 or 32 entries respectively
Keywords
buffer storage; program verification; storage allocation; SPEC programs; atomic units; code coalescing unit; decoded instruction cache; load instructions; load store data communication; memory access instructions; program behavior; Arithmetic; Availability; Bandwidth; Computer aided instruction; Data communication; Data engineering; Decoding; Program processors; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-9099-2
Type
conf
DOI
10.1109/ICCD.1998.727106
Filename
727106
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