Simulating the behaviour of software modules by trace rewriting

Author

Wang, Yabo ; Parnas, D.L.

Author_Institution

Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada

fYear

1993

fDate

17-21 May 1993

Firstpage

14

Lastpage

23

Abstract

The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, the authors plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates the externally observable behavior of the modules specified. They first present the trace assertion method. Then trace rewriting systems are formally defined, and it is shown that trace rewriting, a technique similar to term rewriting, can be applied to implement trace simulation

Keywords

finite state machines; formal specification; rewriting systems; system monitoring; virtual machines; finite state machine; module interface specification; software modules; specification simulation tool; trace rewriting; trace simulator; Automata; Communication standards; Computational modeling; Computer simulation; Discrete event simulation; Formal specifications; History; Software systems; Software tools; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Software Engineering, 1993. Proceedings., 15th International Conference on

Conference_Location

Baltimore, MD

ISSN

0270-5257

Print_ISBN

0-8186-3700-5

Type

conf

DOI

10.1109/ICSE.1993.346059

Filename

346059