A 0.1–5GHz Dual-VCO software-defined ∑Δ frequency synthesizer in 45nm digital CMOS

A wide-band frequency synthesizer architecture for software defined radio applications is presented, based on a dual-VCO SigmaDelta phase locked loop (PLL), with a wide-range modulus programmable divider. The design combines high flexibility to cover several wireless standards, with a scalable implementation, exploiting the capabilities of advanced digital technologies at reduced area costs. The prototype in 1.1-V 45-nm digital CMOS achieves a 4.3 to 10 GHz PLL tuning range, with programmable K_VCO, bandwidth, between 110 and 320 KHz, and current consumption, ranging from 20 to 29 mA. Measured phase noise is -122 dBc/Hz at 2-MHz offset from a 7.2 GHz carrier.