A 3GHz wideband ∑Δ fractional-N synthesizer with voltage-mode exponential CP-PFD

A 3 GHz wideband SigmaDelta fractional-N synthesizer with an exponential settling voltage-mode PFD is presented. The 1 MHz band-width type-I PLL loop utilizes the exponential small-signal settling characteristics of a voltage-mode NMOS (follower) LDO based PFD-CP to reduce in-band quantization noise leakage by more than 13 dB without the need for a noise suppression DAC. The PLL is fabricated on a 0.18 mum CMOS process with less than 20-mA current consumption from 1.8-V power supply. The measured in-band phase noise at 100 kHz is -107 dBc/Hz and out-of-band phase noise at 3 MHz is -130 dBc/Hz. The PLL loop settling time for an accuracy of 0.1 ppm and a frequency step of 45 MHz is less than 10 mus.