Functional Coverage Driven Verification for TAU-MVBC

Functional verification plays a more and more important role in the design flow of intellectual property cores and embedded systems because of the increasing trends in complexity and integrity of embedded systems. To meet the demands of quality assurance and time to market, EDA companies are developing verification methods and tools that involve high-level hardware description language, reusable verification environment and automatic stimulus generation techniques. MVBC is the core controller on the MVB (Multi-functional Vehicle Bus), which acts as the interface of host processor and MVB physical layer. TAU (Telegram Analysis Unit) as a central part of MVBC, performs sending and receiving messages and analyzing received messages cooperated with other components. This paper describes a functional coverage driven verification environment for the verification of TAU-MVBC. According to the Verification Methodology Manual (VMM) for System Verilog, a layered reusable verification environment is developed together with a final coverage report summary. Constrained random stimulus generation technique is applied to narrow down the input vector space and improve functional coverage in a reasonable time. Assertions are utilized to cover function points which can´t be covered by random combinations of input signals.