DocumentCode
2299101
Title
An efficient low-power bus architecture
Author
Rjoub, A. ; Nikolaidis, S. ; Koufopavlou, O. ; Stouraitis, T.
Author_Institution
Dept. of Electr. & Comput. Eng., Patras Univ., Greece
Volume
3
fYear
1997
fDate
9-12 Jun 1997
Firstpage
1864
Abstract
In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained
Keywords
CMOS digital integrated circuits; VLSI; driver circuits; CMOS technology; internal long interconnection line driving; low-power bus architecture; power consumption reduction; reduced voltage swing technique; repeater circuit; swing level; time performance; CMOS technology; Computer architecture; Driver circuits; Energy consumption; Laboratories; MOSFETs; Physics computing; Repeaters; Threshold voltage; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN
0-7803-3583-X
Type
conf
DOI
10.1109/ISCAS.1997.621512
Filename
621512
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