• DocumentCode
    2299138
  • Title

    Simultaneous access renegable priority queues

  • Author

    Subramaniam, P. R Venkata ; Cheng, Kam-Hoi

  • Author_Institution
    Dept. of Comput. Sci., Houston Univ., TX, USA
  • fYear
    1994
  • fDate
    26-29 Oct 1994
  • Firstpage
    370
  • Lastpage
    376
  • Abstract
    A renegable priority queue has been designed on two different types of network. The first design uses hypercube networks, and has a response time and a pipeline cycle time O(log p), where p is the maximum number of processors that may access the design simultaneously. The second design uses reconfigurable meshes with both response time and pipeline cycle time being constants. Each of these designs uses O(p2m) processing elements, and have a capacity of pm, where m is a positive integer
  • Keywords
    data structures; hypercube networks; parallel architectures; pipeline processing; queueing theory; reconfigurable architectures; data structures; hypercube networks; multiprocessors; parallel processing; pipeline cycle time; processing elements; reconfigurable meshes; renegable priority queue; response time; simultaneous access renegable priority queues; Algorithm design and analysis; Computer science; Data structures; Delay; Hypercubes; Parallel processing; Pipelines; Process design; Throughput; Time factors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing, 1994. Proceedings. Sixth IEEE Symposium on
  • Conference_Location
    Dallas, TX
  • Print_ISBN
    0-8186-6427-4
  • Type

    conf

  • DOI
    10.1109/SPDP.1994.346146
  • Filename
    346146
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2299138