Title :
An Error Correction Method for Binary and Multiple-Valued Logic
Author :
Winstead, Chris ; Luo, Yi ; Monzon, Eduardo ; Tejeda, Abiezer
Author_Institution :
Dept. of Electr. & Comput. Eng., Utah State Univ., Logan, UT, USA
Abstract :
This paper presents a method and circuit for correcting faults in logic systems. The method, called "restorative feedback" (RFB), is similar in some respects to triple modular redundancy (TMR), but has an improved error probability with respect to transient errors. Simulation results indicate an improvement by about two orders of magnitude compared to traditional TMR. CMOS circuits are presented for implementing restorative feedback. For binary logic, a dynamic CMOS circuit is considered. For multiple-valued logic, a semi-floating gate implementation is presented.
Keywords :
CMOS integrated circuits; error correction; multivalued logic; CMOS circuits; RFB; TMR; binary logic; error correction method; error probability; multiple-valued logic; restorative feedback; semi-floating gate implementation; triple modular redundancy; Bit error rate; CMOS integrated circuits; Feedback circuits; Integrated circuit modeling; Logic gates; Tunneling magnetoresistance; Fault tolerant logic; error correction;
Conference_Titel :
Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on
Conference_Location :
Tuusula
Print_ISBN :
978-1-4577-0112-2
Electronic_ISBN :
0195-623X
DOI :
10.1109/ISMVL.2011.52
