An analysis of parallel synchronous and conservative asynchronous logic simulation schemes

A recent paper by Bailey (1992) contains a theorem stating that the idealized execution times of unit-delay, synchronous and conservative asynchronous simulations are equal under the conditions that unlimited number of processors are available and the evaluation time of each logic element is equal. Further it is shown that the above conditions result in a lower bound on the execution times of both synchronous and conservative asynchronous simulations. Bailey´s above important conclusions are derived under a strict assumption that the inputs to the circuit remain fixed during the entire simulation. We remove this limitation and by extending the analyses to multi-input, multi-output circuits with an arbitrary number of input events show that the conservative asynchronous simulation executes faster than synchronous simulation in general. Our conclusions are supported by a comparison of the idealized execution times of synchronous and conservative asynchronous algorithms on ISCAS combinational and sequential benchmark circuits