Title :
Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo, Norway
Abstract :
In this paper we present a novel high speed and ultra low-voltage full adder circuit based on ultra low-voltage semi floating-gate CMOS logic. The full adder circuit contains a high speed ultraslow-voltage carry generator circuit and a multiple-valued intermediate representation of the summation. The full adder is suitable for low-voltage serial full adder design. Simulated data presented is valid for a 90nm TSMC CMOS process.
Keywords :
CMOS digital integrated circuits; adders; multivalued logic circuits; thyristor circuits; TSMC CMOS process; high-speed CMOS full adder; multiple-valued intermediate representation; multiple-valued logic; size 90 nm; ultralow-voltage adder; ultralow-voltage semifloating-gate CMOS logic; ultraslow-voltage carry generator circuit; Adders; CMOS integrated circuits; Delay; Inverters; Logic gates; Low voltage; Transistors; Multiple valued; full adder; low votage;
Conference_Titel :
Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on
Conference_Location :
Tuusula
Print_ISBN :
978-1-4577-0112-2
Electronic_ISBN :
0195-623X
DOI :
10.1109/ISMVL.2011.11
