DocumentCode
2299720
Title
Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic
Author
Berg, Y.
Author_Institution
Dept. of Inf., Univ. of Oslo, Oslo, Norway
fYear
2011
fDate
23-25 May 2011
Firstpage
259
Lastpage
262
Abstract
In this paper we present a novel high speed and ultra low-voltage full adder circuit based on ultra low-voltage semi floating-gate CMOS logic. The full adder circuit contains a high speed ultraslow-voltage carry generator circuit and a multiple-valued intermediate representation of the summation. The full adder is suitable for low-voltage serial full adder design. Simulated data presented is valid for a 90nm TSMC CMOS process.
Keywords
CMOS digital integrated circuits; adders; multivalued logic circuits; thyristor circuits; TSMC CMOS process; high-speed CMOS full adder; multiple-valued intermediate representation; multiple-valued logic; size 90 nm; ultralow-voltage adder; ultralow-voltage semifloating-gate CMOS logic; ultraslow-voltage carry generator circuit; Adders; CMOS integrated circuits; Delay; Inverters; Logic gates; Low voltage; Transistors; Multiple valued; full adder; low votage;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on
Conference_Location
Tuusula
ISSN
0195-623X
Print_ISBN
978-1-4577-0112-2
Electronic_ISBN
0195-623X
Type
conf
DOI
10.1109/ISMVL.2011.11
Filename
5954243
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