Data-flow analysis in superscalar computer architecture execution

Author

Zaharieva-Stoyanova, Elena I.

Author_Institution

Dept. of Comput. Syst. & Technol., Tech. Univ. of Gabrovo, Bulgaria

Volume

2

fYear

2003

fDate

1-3 Oct. 2003

Firstpage

622

Abstract

This paper treats the problem of detection of data hazards in superscalar execution. The algorithms of independent instruction detection are represented. They can be used in out-of-order execution logic and code optimised algorithms. The first algorithm uses the platform of Intel Pentium architecture and analyse the IA-32 instruction set. The algorithms is implemented in a software simulator, which represents the way the Intel Pentium processor works. They can be used in software module, which simulates out-of-order execution logic.

Keywords

data flow analysis; instruction sets; optimisation; program processors; reduced instruction set computing; IA-32 instruction set; Intel Pentium processor architecture; RISC architecture; code optimised algorithms; data hazards; data-flow analysis; independent instruction detection algorithm; out-of-order execution logic; software simulator; superscalar computer architecture execution; Analytical models; Computational modeling; Computer architecture; Data analysis; Hazards; Logic; Parallel processing; Pipeline processing; Reduced instruction set computing; Software algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunications in Modern Satellite, Cable and Broadcasting Service, 2003. TELSIKS 2003. 6th International Conference on

Print_ISBN

0-7803-7963-2

Type

conf

DOI

10.1109/TELSKS.2003.1246301

Filename

1246301