• DocumentCode
    2300334
  • Title

    Dynamic hammock predication for non-predicated instruction set architectures

  • Author

    Klauser, Artur ; Austin, Todd ; Grunwald, Dirk ; Calder, Brad

  • Author_Institution
    Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
  • fYear
    1998
  • fDate
    12-18 Oct 1998
  • Firstpage
    278
  • Lastpage
    285
  • Abstract
    Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However certain branches are difficult to predict. One solution to this problem is to evaluate both paths following such a conditional branch. Predicated execution can be used to implement this form of multi-path execution. Predicated architectures fetch and issue instructions that have associated predicates. These predicates indicate if the instruction should commit its result. Predicating a branch reduces the number of branches executed, eliminating the chance of branch misprediction at the cost of executing additional instructions. In this paper, we propose a restricted form of multi-path execution called Dynamic Predication for architectures with little or no support for predicated instructions in their instruction set. Dynamic predication dynamically predicates instruction sequences in the form of a branch hammock concurrently executing both paths of the branch. A branch hammock is a short forward branch that spans a few instructions in the form of an if-then or if-then-else construct we mark these and other constructs in the executable. When the decode stage detects such a sequence, it passes a predicated instruction sequence to a dynamically scheduled execution core. Our results show that dynamic predication can accrue speedups of up to 13%
  • Keywords
    parallel architectures; processor scheduling; Dynamic Predication; branch hammock; branch prediction; conditional branch; if-then; if-then-else; multi-path execution; speculative architectures; Accuracy; Computer architecture; Computer science; Costs; Decoding; Degradation; Dynamic scheduling; Instruction sets; Microcomputers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures and Compilation Techniques, 1998. Proceedings. 1998 International Conference on
  • Conference_Location
    Paris
  • ISSN
    1089-795X
  • Print_ISBN
    0-8186-8591-3
  • Type

    conf

  • DOI
    10.1109/PACT.1998.727261
  • Filename
    727261