FPGA implementation of running DFT for selective harmonics analysis

This paper presents mathematical representation of the Running Discrete Fourier Transform (RDFT) and proposes an architecture for selective harmonics device using RDFT. We used `one multiplier and two adders´ arithmetic modules. The proposed architecture has been implemented on FPGA using Verilog HDL. Since this implementation consumes lesser area, its Discrete Fourier Transform (DFT) representation has efficient hardware complexity in the order of O(N). For real-time harmonics detection and analysis we have used target device Virtex-5 (“xc5vlx110t-2-ff1136”), which is a preferred device in field for modern DSP applications.