Design, simulation and characterization of memory cell array for low power SRAM using 90nm CMOS technology

First, unlike the conventional simple transistor SRAM cell, High Vt Transistor is used in order to reduce stand By leakage power. This is a single port ‘Write Trough Memory’ i.e. whatever data is going to write in a cell could read simultaneously. Since large Bit line capacitance is switched during read and writes operation, power dissipation is maximum during read and writes operation. To reduced the dynamic power the read and write circuitry is designed in such a way that very least no of transistor ‘ON’ at a time. Read and write operation performed when Precharge circuit is off. During Read, When Precharge signal goes to its 90% (Active Low) of its final value. Word line immediately ‘ON’ and goes off as soon as 60mv of bit line difference is achieved. Thus Access and pulldown transistor ‘ON’ for a very short moment of time hence reduced dynamic power.