Design and implementation of parallel hierarchical finite state machines

This paper presents a novel model and method for synthesis of parallel hierarchical finite state machines (PHFSM) that permit to implement algorithms composed of modules in such a way that 1) the modules can be activated from other modules, and 2) more than one module can be activated in parallel. The model combines multiple stack memories interacting with a combinational circuit. The synthesis involves three basic steps: 1) conversion of a given specification to special state transition diagrams; 2) use of the proposed hardware description language templates; 3) synthesis of the circuit from the templates. A number of PHFSMs have been designed, implemented in low-cost commercially available FPGAs, tested, and evaluated. The results of experiments have proven the effectiveness and practicability of the proposed technique for solving real-world problems.