A 30000 gate ECL gate array using advanced single poly technology and four level metal interconnect

Author

Ganschow, George ; Lee, Lun-Hui ; Ho, Larry ; Truong, Mau ; Haas, Fred ; Joshi, Shailendra P. ; Smith, Peter ; Jerome, Rick ; Lahri, R. ; Bouknight, Lyle ; Biswal, Madan ; Lam, Nim

Author_Institution

Nat. Semicond. Corp., Puyallup, WA, USA

fYear

1990

fDate

13-16 May 1990

Abstract

The architecture and fabrication of a 30000 emitter coupled logic (ECL) gate array featuring a 90-ps unloaded gate delay are described. Current mode logic (CML) and ECL macros can be combined on custom-defined chips to minimize power without compromising the performance. The product has a channelless ocean-of-cells architecture permitting 100% cell utilization with ECL 100 K and 10 K I/O interface. The gate array is fabricated using ASPECT-II (advanced single poly emitter coupled technology) with silicided polysilicon local interconnect and four-level metallization.<>

Keywords

application specific integrated circuits; bipolar integrated circuits; cellular arrays; emitter-coupled logic; logic arrays; 90 ps; ASPECT-II; CML; ECL gate array; advanced single poly technology; channelless ocean-of-cells architecture; current mode logic; custom-defined chips; emitter coupled logic; fabrication; four level metal interconnect; multilevel metallisation; polycrystalline Si; silicided polysilicon local interconnect; unloaded gate delay; Delay; Dielectrics; Fabrication; Integrated circuit interconnections; Marine technology; Master-slave; Resistors; Routing; Temperature distribution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA, USA

Type

conf

DOI

10.1109/CICC.1990.124659

Filename

124659