A 150 K-circuit ASIC family using a DRAM technology

Author

Weir, Mark ; Kita, Jay ; Cockerill, Thomas ; Hynek, Paul ; Lepsic, Thomas ; Ta, Trang ; Wong, Bobby ; Woodham, Steven ; Young, Richard

Author_Institution

IBM Gen. Technol. Div., Essex Junction, VT, USA

fYear

1990

fDate

13-16 May 1990

Abstract

The features of a gate-array ASIC family using a CMOS DRAM technology are described. The availability of DRAM, the mix of gate-array and standard-cell circuits, and the choice of using either DLM (double-level metal) or TLM (triple-level metal) provide a designer with options not available in other ASIC families. The associated design system enables design entry, physical design, design verification, and release to manufacturing with as little manual intervention as possible. By using this ASIC family and design system, high-performance chips with up to 253 K-circuits can be designed. This family has been demonstrated with a 128 K-circuit chip

Keywords

CMOS integrated circuits; DRAM chips; application specific integrated circuits; circuit layout CAD; logic CAD; logic arrays; ASIC family; CAD; DRAM technology; circuit library; design entry; design system; design verification; double-level metal; embedded dynamic RAM; gate-array; physical design; standard-cell circuits; triple-level metal; Aluminum; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Integrated circuit technology; Logic design; Manufacturing processes; Random access memory; Surfaces; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124661

Filename

124661