DocumentCode
2302177
Title
DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield
Author
Venkataraman, Srikanth
Author_Institution
Intel
fYear
2007
fDate
39142
Firstpage
5
Lastpage
5
Abstract
Semiconductor yield has traditionally been limited by random particle-defect based issues.However, as the feature sizes reduced to 0.13 micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms.
Keywords
Automatic test pattern generation; Automatic testing; Design for manufacture; Design for testability; Failure analysis; Manufacturing processes; Pattern analysis; Semiconductor device manufacture; Silicon; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location
San Jose, CA, USA
Print_ISBN
0-7695-2795-7
Type
conf
DOI
10.1109/ISQED.2007.61
Filename
4149000
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