Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs

We present a critical study of the impact of gate tunneling currents on the yield of a 65nm PD/SOI SRAM cell. Gate-leakage tunneling currents are obtained from hardware measurements. It is shown that the gate-leakage impact on the cell yield can be non-monotonic, and is appreciable even for non-defective devices. It is also shown that further design optimizations such as the operating voltage or bitline loading can help alleviate the gate-leakage impact on yield. Mixture importance sampling is used to estimate yield, and threshold voltage variations to model random fluctuation effects are extrapolated from hardware