DocumentCode
2302383
Title
Speculative Energy Scheduling for LDPC Decoding
Author
Wang, Weihuang ; Choi, Gwan
Author_Institution
Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX
fYear
2007
fDate
26-28 March 2007
Firstpage
79
Lastpage
84
Abstract
This paper presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in fading channels. The proposed scheme pre-analyzes each received data frame to estimate the maximum number of necessary iterations for the frame convergence. The results are then used to dynamically adjust decoder frequency and switch between multiple-voltage levels; thereby energy use is minimized. This is in contrast to the conventional fixed-iteration decoding schemes that operates at a fixed voltage level regardless the quality of data received. The result is a decoder implementation that provides a judicious trade-off between power consumption and coding gain
Keywords
convergence; decoding; iterative methods; low-power electronics; parity check codes; LDPC; data frame; decoding; fading channels; fixed iteration; frame convergence; low power; speculative energy scheduling; Convergence; Dynamic scheduling; Energy consumption; Frequency; Hardware; Iterative decoding; Parity check codes; Processor scheduling; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7695-2795-7
Type
conf
DOI
10.1109/ISQED.2007.148
Filename
4149015
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