DocumentCode
2302637
Title
Cross Layer Error Exploitation for Aggressive Voltage Scaling
Author
Djahromi, Amin Khajeh ; Eltawil, Ahmed M. ; Kurdahi, Fadi J. ; Kanj, Rouwaida
Author_Institution
UC, Irvine , CA
fYear
2007
fDate
26-28 March 2007
Firstpage
192
Lastpage
197
Abstract
This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3 GPP WCDMA modem
Keywords
CMOS integrated circuits; SRAM chips; logic design; low-power electronics; 32 nm; 6T SRAM failure modes; CMOS 3 GPP WCDMA modem; aggressive voltage scaling; cross layer error exploitation; data redundancy; hardware failures; Circuits and systems; Cross layer design; Hardware; Modems; Multiaccess communication; Power generation; Random access memory; Redundancy; Statistics; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7695-2795-7
Type
conf
DOI
10.1109/ISQED.2007.53
Filename
4149033
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