DocumentCode :
2302800
Title :
Interface Specification Assurance Methods
Author :
Jin, Naiyong ; Ni, Taoyong
Author_Institution :
Software Eng. Inst., East China Normal Univ., Shanghai
fYear :
2007
fDate :
26-28 March 2007
Firstpage :
269
Lastpage :
274
Abstract :
PSL supports property inheritance by verification units. The lack of formal semantics of the inherit operator is an obstacle to reduce the complexity of system design and verification. This paper presents a verification-layer specification assurance tool. Based on the component-based design methodology, we propose a principled organization of component specifications, and apply SAT solvers to verify the consistency of specifications, the compatibility of components, the refinement relation among specifications, and the correctness of specification inheritance. We also discuss the implementation aspect of such a tool
Keywords :
formal verification; hardware description languages; integrated circuit design; component-based methodology; interface specification assurance methods; verification-layer specification assurance tool; Assembly systems; Automata; Circuits; Design methodology; Embedded system; Hardware; Input variables; Master-slave; Protocols; Software engineering; Component-Based Methodology; PSL; SAT; Specification Assurance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2795-7
Type :
conf
DOI :
10.1109/ISQED.2007.93
Filename :
4149046
Link To Document :
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