Variation Aware Timing Based Placement Using Fuzzy Programming

In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical timing analysis and variation aware optimization schemes are required to improve the performance and yield of fabricated circuits. In this paper, we propose a new timing based incremental placement algorithm using fuzzy mathematical programming (FMP) in which the uncertainty due to process variations is modeled using fuzzy numbers. The objective is to minimize the worst negative slack of the circuit with the variations in gate and interconnect delays modeled as triangular fuzzy numbers. In this approach, average and worst case deterministic optimizations are performed to determine the bounds of the problem and then, use these bounds to convert the fuzzy problem into a crisp problem. The crisp model is targeted at maximizing the variation resistance or robustness of the circuit without compromising on the achievable performance of the circuit. The proposed approach being tested on ITC ´99 benchmarks shows an average of 12% improvement when compared to the worst case process variations setting, with a timing yield of 99-100%, as verified through Monte-Carlo simulations