Design-for-Manufacture for Multi Gate Oxide CMOS Process

Author

Lin, Qi ; Ma, Mei ; Vo, Tony ; Fan, Jenny ; Wu, Xin ; Li, Richard ; Li, Xiao-Yu

Author_Institution

Xilinx Inc., San Jose, CA

fYear

2007

fDate

26-28 March 2007

Firstpage

339

Lastpage

343

Abstract

Most of DFM emphasis has been placed on those so called "lithography critical layers" like diffusion, poly, contact and metal layers. However, "non-lithography-critical layers" impact on the manufacture and the yield has not been investigated well. This paper addresses the DFM issue for one of "non-lithography-critical layers", i.e. thick gate oxide layout in dual oxide product, which in this case impacts the product yield significantly. In this paper, a yield loss in a dual oxide FPGA product is analyzed, and the root cause is demonstrated and finally the DFM approaches for gate oxide design and layout are proposed

Keywords

CMOS logic circuits; design for manufacture; integrated circuit yield; design-for-manufacture; dual oxide FPGA product; multigate oxide CMOS process; nonlithography-critical layers; product yield impact; root cause; CMOS logic circuits; CMOS process; Design for manufacture; Etching; Field programmable gate arrays; Guidelines; Lithography; Logic design; Manufacturing; Silicon; DFM; FPGA; layout; multi gate oxide; yield.;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-2795-7

Type

conf

DOI

10.1109/ISQED.2007.58

Filename

4149058