Title :
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations
Author :
Goparaju, Manoj Kumar ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL
Abstract :
Threshold logic gates (TLG) are prone to manufacturing defects that impact weight values which inadvertently affect the functionality of the gate. A method is presented for the design of threshold logic gates to tolerate manufacturing defects to the maximum possible extend. A novel solution is presented for the problem of identifying a fault tolerant k-input TLG for any value of k
Keywords :
fault tolerance; logic design; logic gates; fault tolerance; manufacturing defects; threshold logic gates; Boolean functions; CMOS logic circuits; Computer aided manufacturing; Design methodology; Design optimization; Fault diagnosis; Fault tolerance; Logic design; Logic devices; Logic gates;
Conference_Titel :
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2795-7
DOI :
10.1109/ISQED.2007.12
