A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Author

Seo, K.-I. ; Haran, B. ; Gupta, Deepika ; Guo, Di ; Standaert, T. ; Xie, R. ; Shang, H. ; Alptekin, E. ; Bae, D.-I. ; Bae, G. ; Boye, C. ; Cai, H. ; Chanemougame, D. ; Chao, Roger ; Cheng, K. ; Cho, Jeon-Wook ; Choi, Kwonhue ; Hamieh, B. ; Hong, J.G. ; Ho

fYear

2014

fDate

9-12 June 2014

Firstpage

1

Lastpage

2

Abstract

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um² SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

Keywords

MOSFET; SRAM chips; lithography; low-power electronics; metallisation; silicon-on-insulator; FINFET devices; SRAM bit cell; contacted poly pitch; metallization pitch; multi workfunction gate stack; optical patterning limit; size 10 nm; size 48 nm; size 64 nm; static noise margin; voltage 0.75 V; voltage 140 mV; CMOS integrated circuits; FinFETs; Logic gates; Metals; Random access memory; Substrates; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4799-3331-0

Type

conf

DOI

10.1109/VLSIT.2014.6894342

Filename

6894342