• DocumentCode
    230334
  • Title

    Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

  • Author

    Kim, Yong Sin ; Kodama, Shinsuke ; Mizushima, Y. ; Maeda, Noboru ; Kitada, H. ; Fujimoto, Kenji ; Nakamura, T. ; Suzuki, Daisuke ; Kawai, A. ; Arai, Kenta ; Ohba, Tsuyoshi

  • Author_Institution
    ICE Cube Center, Tokyo Inst. of Technol., Yokohama, Japan
  • fYear
    2014
  • fDate
    9-12 June 2014
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    An ultra-thinning down to 4-μm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-μm was approximately 1-μm within 300-mm wafer. No degradation in terms of retention characteristics and distribution employing 2Gb DRAM wafer was found after ultra-thinning. This suggests that no damage occurred due to thinning processes including wafer bonding and debonding steps. These results indicate good feasibility for multi-stack Wafer-on-Wafer (WOW) processes with the lowest aspect ratio of TSVs and parasitic capacitance, and enable multi-stacking for Tera-scale high density memory.
  • Keywords
    DRAM chips; three-dimensional integrated circuits; wafer bonding; 3D multistack WOW applications; DRAM; TSV; atomic level vacancy; coarse grinding; fine grinding; memory size 2 GByte; multistack wafer-on-wafer processes; parasitic capacitance; retention characteristics; retention distribution; size 300 mm; size 4 mum; size 40 nm; stress relief; terascale high density memory; thinning process; through-silicon via; ultrathinning down; wafer bonding; wafer debonding steps; Degradation; Positrons; Random access memory; Silicon; Stress; Surface treatment; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
  • Conference_Location
    Honolulu, HI
  • ISSN
    0743-1562
  • Print_ISBN
    978-1-4799-3331-0
  • Type

    conf

  • DOI
    10.1109/VLSIT.2014.6894347
  • Filename
    6894347