• DocumentCode
    2303698
  • Title

    General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits

  • Author

    Mi, Ning ; Yan, Boyuan ; Tan, Sheldon X D ; Fan, Jeffrey ; Yu, Hao

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Riverside, CA
  • fYear
    2007
  • fDate
    26-28 March 2007
  • Firstpage
    633
  • Lastpage
    638
  • Abstract
    In this paper, we propose a generalized block structure-preserving reduced order interconnect macromodeling method (BSPRIM). Our approach extends structure-preserving model order reduction (MOR) method SPRIM (Freund, 2004) into more general block forms. We first show how SPRIM-like structure-preserving MOR method can be extended to deal with admittance RLC circuit matrices and show the 2q moments are still matched and symmetry is preserved. We then show that 2q moment matching can´t be achieved when the RLC circuits are driven by both current and voltage sources. The new approach also improves SPRIM by introducing the re-orthonormalization process on the partitioned projection matrix. Then we present our BSPRIM method to deal with more circuit partitions and show the resulting general block structure preserving MOR for linear dynamic circuits formulated in impedance and admittance forms. The reduced models by the proposed BSPRIM will still match the 2q moments and preserve the circuit structure properties like symmetry as SPRIM does. Experimental results demonstrate effectiveness of the proposed methods and it outperforms SPRIM in terms of accuracy with more partitions
  • Keywords
    RLC circuits; interconnections; linear network analysis; reduced order systems; transfer functions; generalized block structure-preserving reduced order interconnect macromodeling method; linear dynamic circuits; partitioned projection matrix; re-orthonormalization process; structure-preserving model order reduction method; Admittance; Circuit simulation; Computational modeling; Impedance; Integrated circuit interconnections; RLC circuits; Signal design; Symmetric matrices; System-on-a-chip; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7695-2795-7
  • Type

    conf

  • DOI
    10.1109/ISQED.2007.85
  • Filename
    4149106