• DocumentCode
    230390
  • Title

    The demonstration of colossal magneto-capacitance and “negative” capacitance effect with the promising characteristics of Jg-EOT and transistor´s performance on Ge (100) n-FETs by the novel magnetic gate stack scheme design

  • Author

    Liao, M.-H. ; Huang, S.C. ; Liu, Charles Y. ; Chen, P.G. ; Kao, S.C. ; Lien, C.

  • Author_Institution
    Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2014
  • fDate
    9-12 June 2014
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Super Jg-EOT gate stack characteristics, ultra-high κ value, and the promising transistor´s performance are achieved on the Ge n-FET by the application of the BaTiO3 as the gate dielectric and the magnetic FePt film as the metal gate. The super Cgate/κ-value is generated by more dipoles in the HK dielectric layer with the coupling of the build-in magnetic field from MG (HK: BaTiO3; MG: magnetic FePt). With the demonstration of this classical “colossal magneto-capacitance” effect in this work, the κ value can be improved ~175% successfully together with the reduction of Jg ~100X and the Ion is improved ~50% accordingly. On the other hand, the “negative” capacitance effect, which is important for the future steeper sub-threshold swing (S.S) device design, is also observed. The novel gate stack scheme (BaTiO3 HK+ FePt MG), proposed in this work, with the super Jg-EOT characteristics, “negative” capacitance phenomenon, and the promising transistor´s performance on the high mobility (Ge) material provides the useful solution for the future low power mobile device design.
  • Keywords
    barium compounds; elemental semiconductors; field effect transistors; germanium; high-k dielectric thin films; iron alloys; low-power electronics; magnetic thin films; platinum alloys; BaTiO3; FePt; Ge; HK dielectric layer; colossal magnetocapacitance; field effect transistors; gate dielectric; low power mobile device design; magnetic film; magnetic gate stack scheme design; metal gate; n-FET; negative capacitance effect; subthreshold swing device design; ultra-high κ gate stack; Capacitance; Dielectrics; Logic gates; Magnetic fields; Magnetic resonance imaging; Perpendicular magnetic anisotropy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
  • Conference_Location
    Honolulu, HI
  • ISSN
    0743-1562
  • Print_ISBN
    978-1-4799-3331-0
  • Type

    conf

  • DOI
    10.1109/VLSIT.2014.6894375
  • Filename
    6894375