Title :
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture
Author :
Adapa, Rajsekhar ; Flanigan, Edward ; Tragoudas, Spyros ; Laisne, Michael ; Cui, Hailong ; Petrov, Tsvetomir
Author_Institution :
Dept. of ECE, Southern Illinois Univ., Carbondale, IL
Abstract :
Non-robust tests for path delay faults (PDFs) have gained importance in industry as a high percentage of PDFs are non-robustly testable in comparison to robustly testable PDFs. In this paper we present a novel function-based method to generate test patterns for the non-robust testable PDFs under the launch-off-capture (LOC) scan architecture. In contrast to a recently proposed function-based method (Flanigan, 2007) which generates LOC tests for the robustly testable paths, the proposed approach presents a new framework which simplifies the test functions and has simpler algorithms for LOC test generation. Experimental results show that the proposed method has less space and time complexity when compared to (Flanigan, 2007), and is scalable to path intensive designs
Keywords :
automatic test pattern generation; fault diagnosis; integrated circuit testing; LOC test generation; function-based test generation; launch-off-capture scan architecture; nonrobust path delay faults; robustly testable paths; Circuit faults; Circuit testing; Clocks; Delay; Electrical fault detection; Flip-flops; Frequency; Hardware; Lab-on-a-chip; Robustness;
Conference_Titel :
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2795-7
DOI :
10.1109/ISQED.2007.81