An Automated and Fast OPC Algorithm for OPC-Aware Layout Design

To reduce design spin time, OPC-unfriendly spots in IC layout should be found out by designer before tape-out. This can be done by firstly running a "trial OPC" step on the layout, followed by running an OPC step to verify the result. In this paper we introduce a new OPC algorithm using an edge bias modeling method. When given a piece of sample post-OPC layout, software based on this algorithm can automatically correct a design with similar recipe but dozens of times faster than traditional model-based method, at cost of some accuracy loss. This makes the algorithm a good choice for "trial OPC"