Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques

Parametric yield has a direct impact on the profit yield of designs. In sub-90nanometer domains, ensuring acceptable parametric yield by corner case analysis has become inaccurate. Increasing clock requirements and process variations, necessitates the use of statistical modeling and analysis techniques for performance optimization. However, the dimensionality of statistical techniques due to the randomness of process variations has continued to grow, resulting in increased design complexity and run-time, and degrading accuracy. Design of standard cell libraries that are tolerant to process variations is still inadequate. This continues to result in expensive re-spins leading to significant design time overhead and low profit yield. In this paper, the authors present a novel technique to build analytical equivalent models, using statistical techniques, for intra-gate variability of physical parameters. This reduces the dimension of the response surface method to model the gate delay. The authors use these models to optimize the gate delay in the presence of process variations. Experimental results show the effectiveness of using the variation tolerant standard cells, resulting in better performance tolerance in designs