Impact of shallow trench isolation on reliability of buried- and surface-channel sub-/spl mu/m PFET

Shallow trench isolation exhibits all the required isolation-technology properties for ULSI. Its high degree of scaleability relies on the fact that its lateral (isolation width) and vertical (isolation depth) dimensions are decoupled due to an almost-ideal box-shape profile of the isolation. A consequence of the abrupt device edge is that a parasitic drain-to-source leakage path can exist at the corner and along the trench sidewall. This paper describes degradation mechanisms of surface-channel (SC) and buried-channel (BC) PFET devices that are directly related with a corner and sidewall parasitic leakage. Both parasitic regions show a characteristic degradation behavior that can limit device reliability for PFETs in the sub-/spl mu/m regime. The necessary processing conditions that overcome this limitation are also given.